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cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 capsense ? express ? button capacitive controllers cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-54606 rev. *e revised november 19, 2010 capsense ? express ? button capacitive controllers features 10/8/6/4 capacitive button input ? robust sensing algorithm ? high sensitivity, low noise ? immunity to rf and ac noise ? low radiated emc noise ? supports wide range of input capacitance, sensor shapes, and sizes target applications ? printers ? cellular handsets ? lcd monitors ? portable dvd players low operating current ? active current: continu ous sensor scan: 1.5 ma ? deep sleep current: 4 a industry's best configurability ? custom sensor tuning, one optional capacitor ? output supports strong drive for led ? output state can be controlled through i 2 c or directly from capsense ? input state ? run time reconfigurable over i 2 c advanced features ? all gpios support led dimming with configurable delay option in cy8c20110 ? interrupt outputs ? user defined inputs ? wake on interrupt input ? sleep control pin ? nonvolatile storage of custom settings ? easy integration into existing pr oducts ? configure output to match system ? no external components required ? world class free configuration tool wide range of operating voltages ? 2.4 v to 2.9 v ? 3.10 v to 3.6 v ? 4.75 v to 5.25 v i 2 c communication ? supported from 1.8 v ? internal pull-up resistor support option ? data rate up to 400 kbps ? configurable i 2 c addressing industrial temperature range: ?40 c to +85 c. available in 16-pin qfn, 8-pin, and 16-pin soic packages overview these capsense express? controllers support four to ten capacitive sensing (capsense) buttons. the device functionality is configured through an i 2 c port and can be stored in onboard nonvolatile memory for automatic loading at power-on. the cy8c20110 is optimized for dimming leds in 15 selectable duty cycles for back light applications. the device can be configured to have up to 10 gpios connected to the pwm output. the pwm duty cycle is programmable for variable led intensities. the four key blocks that make up these devices are: a robust capacitive sensing core with high immunity against radiated and conductive noise, control regi sters with nonvolatile storage, configurable outputs, and i 2 c communications. the user can configure registers with parameters needed to adjust the operation and sensitivity of th e capsense buttons and outputs and permanently store the settings. the standard i 2 c serial communication interface enables the host to configure the device and read sensor information in real time. the i 2 c address is fully configurable without any external hardware strapping. [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 2 of 39 contents pinouts .............................................................................. 3 typical circuits ................................................................. 6 i2c interface ...................................................................... 8 i2c device addressing ........ ........................................ 8 i2c clock stretching .................................................... 8 format for register write and read ........................... 9 operating modes of i2c commands ............................. 10 normal mode ............................................................. 10 setup mode ............................................................... 10 device operation modes ................................................ 10 active mode ........... .............. .............. .............. .......... 10 periodic sleep mode ................................................. 10 deep sleep mode ...................................................... 10 sleep control pin ............................................................ 10 interrupt pin to master ................................................... 10 led dimming .................................................................. 10 led dimming mode 1: change intensity on on/off button status .............................................. 11 led dimming mode 2: flash intensity on on button status ...................................................... 11 led dimming mode 3: hold intensity after on/off button transition ................................ 12 led dimming mode 4: toggle intensity on on/off or off/on button transitions .................... 12 register map ................................................................... 13 capsense express commands ............................... 17 register conventions ................................................ 17 layout guidelines and best practices ......................... 18 capsense button shapes ......................................... 18 button layout design ................................................ 18 recommended via hole placement .......................... 18 example pcb layout design with two capsense buttons and two leds ........................................................... 20 operating voltages ......................................................... 21 capsense constraints ................................................... 21 electrical specifications ................................................ 22 absolute maximum ratings ... .................................... 22 operating temperature ............................................. 22 dc electrical characteristics ........................................ 23 dc chip level specifications .................................... 23 dc gpio specifications ............................................ 23 dc por and lvd specifications .............................. 24 dc flash write specifications ................................... 25 dc i2c specifications ........ ....................................... 25 capsense electrical characteristics ......................... 25 ac electrical specifications .......................................... 26 ac chip-level specifications .................................... 26 ac gpio specifications ............................................ 26 ac i 2 c specifications ................................................ 27 appendix ? examples of frequently used i2c commands ...................................................... 28 ordering information ...................................................... 29 ordering code definitions ...... ....................................... 29 package diagrams .......................................................... 30 acronyms ........................................................................ 32 acronyms used ......................................................... 32 reference documents .................................................... 32 document conventions ................................................. 32 units of measure ....................................................... 32 numeric conventions ............ .................................... 32 glossary .......................................................................... 33 document history page ................................................. 38 sales, solutions, and legal information ...................... 39 worldwide sales and design s upport ......... .............. 39 products .................................................................... 39 psoc solutions ......................................................... 39 [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 3 of 39 pinouts figure 1. 16-pin qfn (no e-pad) [1] table 1. 16-pin qfn (no e-pad) [1, 2] pin no. pin name description 1 gp0[0] configurable as capsense or gpio 2 gp0[1] configurable as capsense or gpio 3i 2 c scl i 2 c clock 4i 2 c sda i 2 c data 5 gp1[0] configurable as capsense or gpio 6gp1[1] [3] configurable as capsense or gpio 7v ss ground connection 8gp1[2] [3] configurable as capsense or gpio 9 gp1[3] configurable as capsense or gpio 10 gp1[4] configurable as capsense or gpio 11 xres active high external reset with internal pull-up 12 gp0[2] configurable as capsense or gpio 13 v dd supply voltage 14 gp0[3] configurable as capsense or gpio 15 csint integrating capacitor input. the ex ternal capacitance is required only if 5:1 snr cannot be achieved. typical range is 1 nf to 4.7 nf 16 gp0[4] configurable as capsense or gpio ? qfn notes 1. cy8c20110 (10 buttons) / cy8c20180 (8 buttons) / cy8c20160 (6 buttons) / cy8c20140 (4 buttons) 2. 8/6/4 available configurable ios can be configured to any of the 10 ios of the package. after any of the 8/6/4 ios are chosen , the remaining 2/4/6 ios of the package are not available for any functionality. 3. avoid using gp1[1] and gp1[2] for driving leds. these two pins have special functions during power-up which is used at factor y. leds connected to these two pins blink during the power-up of the device. [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 4 of 39 figure 2. 16-pin soic [4] table 2. 16-pin soic [4, 5] pin no name description 1 gp0[3] configurable as capsense or gpio 2 csint integrating capacitor input . the external capacitance is required only if 5:1 snr cannot be achieved. typical range is 1 nf to 4.7 nf 3 gp0[4] configurable as capsense or gpio 4 gp0[0] configurable as capsense or gpio 5 gp0[1] configurable as capsense or gpio 6i 2 c scl i 2 c clock 7i 2 c sda i 2 c data 8 gp1[0] configurable as capsense or gpio 9gp1[1] [6] configurable as capsense or gpio 10 v ss ground connection 11 gp1[2] [6] configurable as capsense or gpio 12 gp1[3] configurable as capsense or gpio 13 gp1[4] configurable as capsense or gpio 14 xres active high external reset with internal pull-up 15 gp0[2] configurable as capsense or gpio 16 v dd supply voltage ? notes 4. cy8c20110 (10 buttons) / cy8c20180 (8 buttons) / cy8c20160 (6 buttons) / cy8c20140 (4 buttons) 5. 8/6/4 available configurable ios can be configured to any of the 10 ios of the package. after any of the 8/6/4 ios are chosen , the remaining 2/4/6 ios of the package are not available for any functionality. 6. avoid using gp1[1] and gp1[2] for driving leds. these two pins have special functions during power-up which is used at factor y. leds connected to these two pins blink during the power-up of the device. [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 5 of 39 figure 3. pin diagram ? 8-pin soic ? cy8c20142 (4 button) table 3. pin definitions ? 8- pin soic ? cy8c20142 (4 button) important note for information on the preferred dimensions for mounti ng qfn packages, see the "application notes for surface mount assembly of amkor's microleadframe (mlf) packages" available at http://www.amkor.com . pin no name description 1v ss ground 2i 2 c scl i 2 c clock 3i 2 c sda i 2 c data 4gp1[0] [7] configurable as capsense or gpio 5gp1[1] [7] configurable as capsense or gpio 6 gp0[0] configurable as capsense or gpio 7 gp0[1] configurable as capsense or gpio 8v dd supply voltage ? note 7. avoid using gp1[0] and gp1[1] for driving led. these two pins have special functions during power up which is used at factory . leds connected to these two pins will blink during power up of the device. [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 6 of 39 typical circuits figure 4. circuit 1 ? five buttons and five leds with i 2 c interface figure 5. circuit 2 ? two buttons and two leds with i 2 c interface ? c2 0.1uf vdd_ce vdd_ce r5 560e d1 led r7 560e d2 led vdd_ce b1 r13 560e r14 560 e b0 c1 1. 2n f vd d_c e u1 cy8c20110 gpo[0] 1 gpo[1] 2 i2c_scl 3 i2c_sda 4 gp1[2] 8 vs s 7 gp 1[ 1] 6 gp1[0] 5 gp 1[ 3] 9 gp 1[ 4] 10 xr e s 11 gpo[2] 12 vdd 13 gp0 [ 3] 14 csint 15 gpo[ 4 ] 16 i2c comm r10 330e interface r8 330e r3 4.7k vdd_ ce r4 4. 7k capsense sensor b2 r1 560 e b3 r2 560e b4 r6 560e r9 560e d3 led vdd_ce r11 560e d4 led r12 560 e d5 led capsense sensor capsense sensor [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 7 of 39 figure 6. circuit 3 ? compatibility with 1.8 v i 2 c signaling note 1.8 v vdd_i2c vdd_ce and 2.4 v vdd_ce 5.25 v figure 7. circuit 4 ? powering down capsense express device for low power requirements for low power requirements, if v dd is to be turned off, this concept can be used. the requirement is that the v dds of capsense express, i 2 c pull-ups, and leds should be from the sa me source such that turning off the v dd ensures that no signal is applied to the device while it is unpowered. the i 2 c signals should not be driven high by the master in this situation. if a port pin or group of port pins of the master can cater to the power supply requirements of the circuit, the ldo can be avoided. master or host ldo capsense express i2c pull ups led i2c bus sda scl vdd output output enable [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 8 of 39 i 2 c interface the capsense express devices support the industry standard i 2 c protocol, which can be used for: configuring the device reading the status and dat a registers of the device controlling device operation executing commands the i 2 c address can be modified during configuration. i 2 c device addressing the device uses a seven bit addressing protocol. the i 2 c data transfer is always initiated by t he master sending a one byte address: the first 7 bits contain the address and the lsb indicates the data transfer direction. zero in the lsb bit indicates the write transaction from master and one indicates read transfer by the mast er. the following table shows examples for different i 2 c addresses. i 2 c clock stretching ?clock stretching? or ?bus stalling? in i 2 c communication protocol is a state in which the slave holds the scl line low to indicate that it is busy. in this condition, the master is expected to wait till the scl is released by the slave. when an i 2 c master communicates wit h the capsense express device, the capsense express stalls the i 2 c bus after the reception of each byte (that is, just before the ack/nak bit) until processing of the byte is complete and critical internal functions are executed. use a fully i 2 c compliant master to communicate with the capsense express device. if the i 2 c master does not support clock stretching (a bit banged software i 2 c master), the master must wait for a specific amount of time (as specified in ?format for register write and read? on page 9) for each register write and read operation before the next bit is transmitted. the i 2 c master must check the scl status (it should be high) before the i 2 c master initiates any data transfer with capsense express. if the master fails to do so and continues to communicate, the communication is erroneous. the following diagrams represent the ack time delays shown in ?format for register write and read? on page 9 for write and read. table 4. i 2 c address examples 7-bit slave address d7 d6 d5 d4 d3 d2 d1 d0 8-bit slave address 1 00000 0 10(w) 02 1 00000 0 11(r) 03 75 10010 1 10(w) 96 75 10010 1 11(w) 97 [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 9 of 39 figure 8. write ack time representation [8] figure 9. read ack time representation [9] format for register write and read register write format register read format legends : notes 8. time to process the received data. 9. time taken for the device to send next byte. start slave addr + w areg addr adata adata a . . . . . data a stop start slave addr + w areg addr astop start slave addr + r a data a data a . . . . . data nstop master a - ack slave n- nak [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 10 of 39 operating modes of i 2 c commands normal mode in normal mode of operation, the acknowledgment time is optimized. the timings remain approximately the same for different configurations of the slave. to reduce the acknowledgment times in normal mode, the registers 0x06?0x09, 0x0c, 0x0d, 0x10?0x17, 0x50, 0x51, 0x57?0x60, 0x7e are given only read access. write to these registers can be done only in setup mode. setup mode all registers have read and write access (except those which are read only) in this mode. the acknowledgment times are longer compared to normal mode. when capsense scanning is disabled (command code 0x0a in command register 0xa0), the acknowledgment times can be improved to values similar to the normal mode of operation. device operation modes capsense express devices are conf igured to operate in any of the following three modes to meet different power consumption requirements: active mode periodic sleep mode deep sleep mode active mode in the active mode, all the devi ce blocks including the capsense sub system are powered. typical ac tive current consumption of the device across the operating voltage range is 1.5 ma. periodic sleep mode sleep mode provides an intermediate power operation mode. it is enabled by configuring the corresponding device registers (0x7e, 0x7f). the device goes into sleep after there is no event for stay awake counter (reg 0x80) number of sleep intervals. the device wakes up on sleep interval and it scans the capacitive sensors before going back to sleep again. if any sensor is active, then the device wakes up. the device can also wake up from sleep mode with a gpio interrupt. the following sleep intervals are supported in capsense express. the sleep interval is configured through registers. 1.95 ms (512 hz) 15.6 ms (64 hz) 125 ms (8 hz) 1 s (1 hz) deep sleep mode deep sleep mode provides the lowest power consumption because there is no operation running. all capsense scanning is disabled during this mode. in this mode, the device wakes up only using an external gpio in terrupt. a sleep timer interrupt cannot wake up a device from de ep sleep mode. this is treated as a continuous sleep mode without periodic wakeups. refer to the application note ?capsense express power and sleep considerations? - an44209 for details on different sleep modes. to get the lowest power during this mode the sleep timer frequency should be set to 1 hz. sleep control pin the devices require a dedicated sleep control pin to enable reliable i 2 c communication in case any sleep mode is enabled. this is achieved by pulling the sleep control pin low to wake up the device and start i 2 c communication. the sleep control pin can be configured on any gpio. interrupt pin to master to inform the master of any button press a gpio can be configured as interrupt output and all capsense buttons can be connected to this gpio with an or logic operator. this can be configured using the software tool. led dimming to change the brightness and in tensity of the leds, the host master (mcu, mpu, dsp, and so on) must send i 2 c commands and program the pwm registers to enable output pins, set duty cycle, and mode configuration. the single pwm source is connected to all gpio pins and has a common user defined duty cycle. each pwm enabled pin has two possible outputs: pwm and 0/1 (depending on the config uration). four different modes of led dimming are possible, as shown in ?led dimming mode 1: change intensity on on/off button status? on page 11 to ?led dimming mode 4: toggle intensity on on/off or off/on button transitions? on page 12. the operation mode and duty cycle of the pwm enabled pins is common. this means that one pin cannot behave as in mode 1 and another pin as in mode 2. [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 11 of 39 led dimming mode 1: change intensity on on/off button status led dimming mode 2: flash intensity on on button status ? ? [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 12 of 39 led dimming mode 3: hold intensity after on/off button transition led dimming mode 4: toggle intensity on on/off or off/on button transitions note led dimming is available only in cy8c20110. ? ? [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 13 of 39 register map name register address (in hex) access writable only in setup mode [10] factory default values of registers (in hex) i2c max ack time in normal mode (ms) i2c max ack time in setup mode (ms) input_port0 00 r ? 00 0.1 ? input_port1 01 r ? 00 0.1 ? status_por0 02 r ? 00 0.1 ? status_por1 03 r ? 00 0.1 ? output_port0 04 w ? 00 0.1 ? output_port1 05 w ? 00 0.1 ? cs_enabl0 06 rw yes 00 ? 11 cs_enable 07 rw yes 00 ? 11 gpio_enable0 08 rw yes 00 ? 11 gpio_enable1 09 rw yes 00 ? 11 inversion_mask0 0a rw ? 00 0.11 ? inversion_mask1 0b rw ? 00 0.11 ? int_mask0 0c rw yes 00 ? 11 int_mask1 0d rw yes 00 ? 11 status_hold_msk0 0e rw ? 03/1f [11] 0.11 ? status_hold_msk1 0f rw ? 03/1f [11] 0.11 ? dm_pull_up0 10 rw yes 00 ? 11 dm_strong0 11 rw yes 00 ? 11 dm_highz0 12 rw yes 00 ? 11 dm_od_low0 13 rw yes 00 ? 11 dm_pull_up1 14 rw yes 00 ? 11 dm_strong1 15 rw yes 00 ? 11 dm_highz1 16 rw yes 00 ? 11 dm_od_low1 17 rw yes 00 ? 11 pwm_enable0 [12] 18 rw ? 00 0.1 ? pwm_enable1 [12] 19 rw ? 00 0.1 ? pwm_mode_dc [12] 1a rw ? 00 0.1 ? pwm_delay [12] 1b rw ? 00 0.1 ? op_sel_00 1c rw ? 00 0.12 11 opr1_prt0_00 1d rw ? 00 0.12 11 opr1_prt1_00 1e rw ? 00 0.12 11 opr2_prt0_00 1f rw ? 00 0.12 11 opr2_prt1_00 20 rw ? 00 0.12 11 op_sel_01 21 rw ? 00 0.12 11 opr1_prt0_01 22 rw ? 00 0.12 11 opr1_prt1_01 23 rw ? 00 0.12 11 opr2_prt0_01 24 rw ? 00 0.12 11 opr2_prt1_01 25 rw ? 00 0.12 11 op_sel_02 26 rw ? 00 0.12 11 opr1_prt0_02 27 rw ? 00 0.12 11 opr1_prt1_02 28 rw ? 00 0.12 11 notes 10. these registers are writable only after entering into setup mode. all the other registers available for read and write in no rmal as well as in setup mode. 11. the factory defaults of reg 0x0e and 0x0f is 0x03 for 20142 device and 0x1f for 20140/60/80/10 devices. 12. these registers are available only in cy8c20110. [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 14 of 39 name register address (in hex) access writable only in setup mode [13] factory default values of registers (in hex) i2c max ack time in normal mode (ms) i2c max ack time in setup mode (ms) opr2_prt0_02 29 rw ? 00 0.12 11 opr2_prt1_02 2a rw ? 00 0.12 11 op_sel_03 2b rw ? 00 0.12 11 opr1_prt0_03 2c rw ? 00 0.12 11 opr1_prt1_03 2d rw ? 00 0.12 11 opr2_prt0_03 2e rw ? 00 0.12 11 opr2_prt1_03 2f rw ? 00 0.12 11 op_sel_04 30 rw ? 00 0.12 11 opr1_prt0_04 31 rw ? 00 0.12 11 opr1_prt1_04 32 rw ? 00 0.12 11 opr2_prt0_04 33 rw ? 00 0.12 11 opr2_prt1_04 34 rw ? 00 0.12 11 op_sel_10 35 rw ? 00 0.12 11 opr1_prt0_10 36 rw ? 00 0.12 11 opr1_prt1_10 37 rw ? 00 0.12 11 opr2_prt0_10 38 rw ? 00 0.12 11 opr2_prt1_10 39 rw ? 00 0.12 11 op_sel_11 3a rw ? 00 0.12 11 opr1_prt0_11 3b rw ? 00 0.12 11 opr1_prt1_11 3c rw ? 00 0.12 11 opr2_prt0_11 3d rw ? 00 0.12 11 opr2_prt1_11 3e rw ? 00 0.12 11 op_sel_12 3f rw ? 00 0.12 11 opr1_prt0_12 40 rw ? 00 0.12 11 opr1_prt1_12 41 rw ? 00 0.12 11 opr2_prt0_12 42 rw ? 00 0.12 11 opr2_prt1_12 43 rw ? 00 0.12 11 op_sel_13 44 rw ? 00 0.12 11 opr1_prt0_13 45 rw ? 00 0.12 11 opr1_prt1_13 46 rw ? 00 0.12 11 opr2_prt0_13 47 rw ? 00 0.12 11 opr2_prt1_13 48 rw ? 00 0.12 11 op_sel_14 49 rw ? 00 0.12 11 opr1_prt0_14 4a rw ? 00 0.12 11 opr1_prt1_14 4b rw ? 00 0.12 11 opr2_prt0_14 4c rw ? 00 0.12 11 opr2_prt1_14 4d rw ? 00 0.12 11 cs_noise_th 4e rw ? 28 0.11 11 cs_bl_upd_th 4f rw ? 64 0.11 11 cs_setl_time 50 rw yes a0 ? 35 cs_oth_set 51 rw yes 00 ? 35 cs_hysterisis 52 rw ? 0a 0.11 11 note 13. these registers are writable only after entering into setup mode. all the other registers available for read and write in no rmal as well as in setup mode. register map (continued) [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 15 of 39 name register address (in hex) access writable only in setup mode [14] factory default values of registers (in hex) i2c max ack time in normal mode (ms) i2c max ack time in setup mode (ms) cs_debounce 53 rw ? 03 0.11 11 cs_neg_noise_th 54 rw ? 14 0.11 11 cs_low_bl_rst 55 rw ? 14 0.11 11 cs_filtering 56 rw ? 20 0.11 11 cs_scan_pos_00 57 rw yes ff ? 11 cs_scan_pos_01 58 rw yes ff ? 11 cs_scan_pos_02 59 rw yes ff ? 11 cs_scan_pos_03 5a rw yes ff ? 11 cs_scan_pos_04 5b rw yes ff ? 11 cs_scan_pos_10 5c rw yes ff ? 11 cs_scan_pos_11 5d rw yes ff ? 11 cs_scan_pos_12 5e rw yes ff ? 11 cs_scan_pos_13 5f rw yes ff ? 11 cs_scan_pos_14 60 rw yes ff ? 11 cs_finger_th_00 61 rw ? 64 0.14 11 cs_finger_th_01 62 rw ? 64 0.14 11 cs_finger_th_02 63 rw ? 64 0.14 11 cs_finger_th_03 64 rw ? 64 0.14 11 cs_finger_th_04 65 rw ? 64 0.14 11 cs_finger_th_10 66 rw ? 64 0.14 11 cs_finger_th_11 67 rw ? 64 0.14 11 cs_finger_th_12 68 rw ? 64 0.14 11 cs_finger_th_13 69 rw ? 64 0.14 11 cs_finger_th_14 6a rw ? 64 0.14 11 cs_idac_00 6b rw ? 0a 0.14 11 cs_idac_01 6c rw ? 0a 0.14 11 cs_idac_02 6d rw ? 0a 0.14 11 cs_idac_03 6e rw ? 0a 0.14 11 cs_idac_04 6f rw ? 0a 0.14 11 cs_idac_10 70 rw ? 0a 0.14 11 cs_idac_11 71 rw ? 0a 0.14 11 cs_idac_12 72 rw ? 0a 0.14 11 cs_idac_13 73 rw ? 0a 0.14 11 cs_idac_14 74 rw ? 0a 0.14 11 75 [15] 76 [15] 77 [15] 78 [15] i2c_addr_lock 79 rw ? 01 0.11 11 device_id 7a r ? 42/40/60/80/10 [16] 0.11 11 device_status 7b r ? 03 0.11 11 i2c_addr_dm 7c rw ? 00 0.11 11 notes 14. these registers are writable only after entering into setup mode. all the other registers available for read and write in no rmal as well as in setup mode. 15. the register 0x75?0x78, 0x7d and 0x8a?0x8d are reserved. 16. the device id for different devices are tabulated in ta b l e 5 . register map (continued) [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 16 of 39 note all the ack times specified are maximum values with a ll buttons enabled and filer enabled with maximum order. name register address (in hex) access writable only in setup mode [17] factory default values of registers (in hex) i2c max ack time in normal mode (ms) i2c max ack time in setup mode (ms) 7d [18] sleep_pin 7e rw yes 00 0.1 11 sleep_ctrl 7f rw ? 00 0.1 11 sleep_sa_cntr 80 rw ? 00 0.1 11 cs_read_button 81 rw ? 00 0.12 11 cs_read_blm 82 r ? 00 0.12 11 cs_read_bll 83 r ? 00 0.12 11 cs_read_diffm 84 r ? 00 0.12 11 cs_read_diffl 85 r ? 00 0.12 11 cs_read_rawm 86 r ? 00 0.12 11 cs_read_rawl 87 r ? 00 0.12 11 cs_read_statusm 88 r ? 00 0.12 11 cs_read_statusl 89 r ? 00 0.12 11 8a [18] 8b [18] 8c [18] 8d [18] command_reg a0 w ? 00 0.1 11 table 5. device ids part number device id cy8c 20142 42 cy8c 20140 40 cy8c 20160 60 cy8c 20180 80 cy8c 20110 10 register map (continued) notes 17. these registers are writable only after entering into setup mode. all the other registers available for read and write in no rmal as well as in setup mode. 18. the register 0x75?0x78, 0x7d and 0x8a?0x8d are reserved. [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 17 of 39 capsense express commands register conventions this table lists the register conventions that are specific to this section. command [19] description executable mode duration the device is not accessible after ack (in ms) w 00 a0 00 get firmware revision setup/normal 0 w 00 a0 01 store current config uration to nvm setup/normal 120 w 00 a0 02 restore factory c onfiguration setup/normal 120 w 00 a0 03 write nvm por defaults setup/normal 120 w 00 a0 04 read nvm por defaults setup/normal 5 w 00 a0 05 read current configurations (ram) setup/normal 5 w 00 a0 06 reconfigure device (por) setup 5 w 00 a0 07 set normal mode of operation setup/normal 0 w 00 a0 08 set setup mode of operation setup/normal 0 w 00 a0 09 start scan setup/normal 10 w 00 a0 0a stop scan setup/normal 5 w 00 a0 0b get capsense scan status setup/normal 0 note 19. the ?w? indicates the write transfer. the next byte of data represents the 7-bit i2c address. convention description rw register has both read and write access r register has only read access [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 18 of 39 layout guidelines and best practices capsense button shapes button layout design x: button to ground clearance (refer to table 6 on page 18 ) y: button to button clearance (refer to table 6 on page 18 ) recommended via hole placement ? 1 button shape ? ? solid round pattern, round with led hole, rectangle with round corners 2 button size 5 mm 15 mm 10 mm 3 button-button spacing equal to button ground clearance ? 8 mm [x] 4 button ground clearance 0.5 mm 2 mm button ground clearance = overlay thickness [y] 5 ground flood-top layer ? ? hatched ground 7-m il trace and 45-mil grid (15% filling) 6 ground flood-bottom layer ? ? hatched ground 7 -mil trace and 70-mil grid (10% filling) 7 trace length from sensor to psoc-buttons ? 200 mm < 100 mm 8 trace width 0.17 mm 0.20 mm 0.17 mm (7-mil) [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 19 of 39 9 trace routing ? ? traces should be rout ed on the non sensor side. if any non capsense trace crosses capsense trace, ensure that intersection is orthogonal. 10 via position for the sensors ? ? via should be placed near the edge of the button/slider to reduce trace length thereby increasing sensitivity. 11 via hole size for sensor traces ? ? 10-mil 12 number of vias on sensor trace 1 2 1 13 capsense series resistor placement ? 10 mm place capsense series resistors close to psoc for noise suppression. capsense resistors have highest priority place them first. 14 distance between any capsense trace to ground flood 10-mil 20-mil 20-mil 15 device placement ? ? mount the device on the layer opposite to sensor. the capsense trace length betwe en the device and sensors should be minimum 16 placement of components in 2-layer pcb ? ? top layer ? sensor pads and bottom layer ? psoc, other components, and traces. 17 placement of components in 4-layer pcb ? ? top layer ? sensor pads, second layer ? capsense traces, third layer ? hatched ground, bottom layer ? psoc, other components, and non capsense traces 18 overlay thickness-buttons 0 mm 2 mm 1 mm 19 overlay material ? ? should to be non c onductive material. glass, abs plastic, formica 20 overlay adhesives ? ? adhesive should be non conductive and dielectrically homogenous. 467mp and 468mp adhesives made by 3m are recommended. 21 led back lighting ? ? cut a hole in the sensor pad and use rear mountable leds. refer the pcb layout below. 22 board thickness ? ? standard board thickness for capsense fr4 based designs is 1.6 mm. table 6. recommended layout guidelines and best practices (continued) sl category min max recommendations/remarks [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 20 of 39 example pcb layout design with two capsense buttons and two leds figure 10. top layer figure 11. bottom layer [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 21 of 39 operating voltages for details on i 2 c 1x ack time, refer to ?register map? on page 13 and ?capsense express commands? on page 17. i 2 c 4x ack time is approximately four times the values mentioned in these tables. capsense constraints parameter min typ max units notes parasitic capacitance (c p ) of the capsense sensor ? ? 30 pf overlay thickness 0 1 2 mm all layout best practices followed, properly tuned, and noise free condition. supply voltage variation (v dd )?? 5%? [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 22 of 39 electrical specifications absolute maximum ratings parameter description min typ max unit notes t stg storage temperature ?55 25 +100 c higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c (0 c to 50 c). extended duration storage temperatures above 65 c degrade reliability t baketemp bake temperature ? 125 see package label o c t baketime bake time see package label ? 72 hours t a ambient temperature with power applied ?40 ? +85 c v dd supply voltage on v dd relative to v ss ?0.5 ? +6.0 v v io dc input voltage v ss ? 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tristate v ss ? 0.5 ? v dd + 0.5 v i mio maximum current into any gpio pin ?25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd lu latch-up current ? ? 200 ma operating temperature parameter description min typ max unit notes t a ambient temperature ?40 ? +85 c t j junction temperature ?40 ? +100 c [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 23 of 39 dc electrical characteristics dc gpio specifications dc chip level specifications parameter description min typ max unit notes v dd supply voltage 2.40 ? 5.25 v i dd supply current ? 1.5 2.5 ma conditions are v dd = 3.10 v, t a = 25 c isb deep sleep mode current with por and lvd active ?2.6 4 av dd = 2.55 v, 0 c < ta < 40 c isb deep sleep mode current with por and lvd active ?2.8 5 av dd = 3.3 v, ?40 c < ta < 85 c isb deep sleep mode current with por and lvd active ?5.26.4av dd = 5.25 v, ?40 c < ta < 85 c table 7. 5-v and 3.3-v dc gpio specifications this table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, 3.10 v to 3.6 v and ?40 c < t a < 85 c. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. parameter description min typ max unit notes v oh1 high output voltage on port 0 pins v dd ? 0.2 ? ? v i oh < 10 a, v dd > 3.10 v, maximum of 20 ma source current in all i/os. v oh2 high output voltage on port 0 pins v dd ? 0.9 ? ? v i oh = 1 ma, v dd > 3.10 v, maximum of 20 ma source current in all i/os. v oh3 high output voltage on port 1 pins v dd ? 0.2 ? ? v i oh < 10 a, v dd > 3.10 v, maximum of 20 ma source current in all i/os. v oh4 high output voltage on port 1 pins v dd ? 0.9 ? ? v i oh = 5 ma, v dd > 3.10 v, maximum of 20 ma source current in all i/os. v ol low output voltage ? ? 0.75 v i ol = 20 ma/pin, v dd > 3.10, maximum of 40/60 ma sink current on even port pins and of 40/60 ma sink current on odd port pins. [20] i oh1 high output current on port 0 pins 0.01 ? 1 ma v dd 3.1 v, maximum of 20 ma source current in all ios i oh2 high output current on port 1 pins 0.01 ? 5 ma v dd 3.1 v, maximum of 20 ma source current in all ios i ol low output current ? ? 20 ma v dd 3.1 v, maximum of 60 ma sink current on pins p0_2, p1_2, p1_3, p1_4 and 60 ma sink current on pins p0_0, p0_1, p0_3, p0_4, p1_0, p1_1 v il input low voltage ? ? 0.75 v v dd = 3.10 v to 3.6 v. v ih input high voltage 1.6 ? ? v v dd = 3.10 v to 3.6 v. v il input low voltage ? ? 0.8 v v dd = 4.75 v to 5.25 v. v ih input high voltage 2.0 ? ? v v dd = 4.75 v to 5.25 v. v h input hysteresis voltage ? 140 ? mv ? i il input leakage ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input 0.5 1.7 5 pf package and pin dependent. temp = 25 c. c out capacitive load on pins as output 0.5 1.7 5 pf package and pin dependent. temp = 25 c. [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 24 of 39 notes 20. the maximum sink current is 40 ma for 20140 and 20142 device s and for all other devices the maximum sink current is 60 ma 21. the maximum sink current per port is 20 ma for 20140 and 20142 devices and for all other devices the maximum sink current is 30 ma. table 8. 2.7-v dc gpio specifications parameter description min typ max unit notes v oh1 high output voltage on port 0 pins v dd ? 0.2 ? ? v i oh <10 a, maximum of 10 ma source current in all ios. v oh2 high output voltage on port 0 pins v dd ? 0.5 ? ? v i oh = 0.2 ma, maximum of 10 ma source current in all ios. v oh3 high output voltage on port 1 pins v dd ? 0.2 ? ? v i oh <10 a, maximum of 10 ma source current in all ios. v oh4 high output voltage on port 1 pins v dd ? 0.5 ? ? v i oh = 2 ma, maximum of 10 ma source current in all ios. v ol1 low output voltage ? ? 0.75 v i ol = 10 ma/pin, v dd > 3.10, maximum of 20/30 ma sink current on even port pins and of 20/30 ma sink current on odd port pins. [21] i oh high output current 0.01 ? 2 ma v dd < 2.9 v, maximum of 10 ma source current in all ios i ol1 low output current on port 0 pins ? ? 10 ma v dd < 2.9 v, maximum of 30 ma sink current on pins p0_2, p1_2, p1_3, p1_4 and 30 ma sink current on pins p0_0, p0_1, p0_3, p0_4, p1_0, p1_1 i ol2 low output current ? ? 20 ma v dd < 2.9 v, maximum of 50 ma sink current on pins p0_2, p1_2, p1_3, p1_4 and 50 ma sink current on pins p0_0, p0_1, p0_3, p0_4, p1_0, p1_1 v il input low voltage ? ? 0.75 v v dd = 2.4 to 2.90 v and 3.10 v to 3.6 v. v ih1 input high voltage 1.4 ? ? v v dd = 2.4 to 2.7 v. v ih2 input high voltage 1.6 ? ? v v dd = 2.7 to 2.90 v and 3.10 v to 3.6 v. v h input hysteresis voltage ? 60 ? mv i il input leakage ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input 0.5 1.7 5 pf package and pin dependent. te m p = 2 5 c . c out capacitive load on pins as output 0.5 1.7 5 pf package and pin dependent. te m p = 2 5 c dc por and lvd specifications parameter description min typ max unit notes v ppor0 v ppor1 v dd value for ppor trip v dd = 2.7 v v dd = 3.3 v, 5 v ? ? 2.36 2.60 2.40 2.65 v v v dd must be greater than or equal to 2.5 v during startup or internal reset. v lvd0 v lvd2 v lvd6 v dd value for lvd trip v dd = 2.7 v v dd = 3.3 v v dd = 5 v 2.39 2.75 3.98 2.45 2.92 4.05 2.51 2.99 4.12 v v v [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 25 of 39 dc flash write specifications this table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < ta < 85 c, 3.10 v to 3.6 v and ?40 c < ta < 85 c or 2.4 v to 2.90 v and ?40 c < ta < 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c. these ar e for design guidance only. flash endurance and retention specificat ions are valid only within the range: 25 c 20 c during the flash write operation. it is at the us er?s own risk to operate out of this temperature range. if flash writing is done out of this temperature range, th e endurance and data retention reduces. dc i 2 c specifications this table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, 3.10 v to 3.6 v and ?40 c < t a < 85 c. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. capsense electrical characteristics symbol description min typ max units notes v ddiwrite supply voltage for flash write operations 2.7 ? ? v i ddp supply current for flash write operations ? 5 25 ma flash enpb flash endurance 50,000 [23] ? ? ? erase/write cycles flash dr flash data retention 10 ? ? years table 9. dc i 2 c specifications [22] symbol description min typ max units notes v ili2c input low level ? ? 0.3 v dd v 2.4 v v dd 2.9 v 3.1 v v dd 3.6 v ? ? 0.25 v dd v4.75 v v dd 5.25 v v ihi2c input high level 0.7 v dd ? ? v 2.4 v v dd 5.25 v v olp low output voltage ? ? 0.4 v i ol = 5 ma/pin c i2c capacitive load on i 2 c pins 0.5 1.7 5 pf package and pin dependent. temp = 25 c. r pu pull-up resistor 4 5.6 8 k ? max (v) typ (v) min (v) conditions for supply voltage result 3.6 3.3 3.1 <2.9 the device automatically reconf igures itself to work in 2.7 v mode of operation. >2.9 or <3.10 this range is not recommended for capsense usage. 2.90 2.7 2.45 <2.45 v the scanning for capsense parameters shuts down until the voltage returns to over 2.45 v. >3.10 the device automatically reconfigur es itself to work in 3.3 v mode of operation. <2.4 v the device goes into reset. 5.25 5.0 4.75 <4.73 v the scanning for capsense parameters shuts down until the voltage returns to over 4.73 v. notes 22. all gpio meet the dc gpio v il and v ih specifications found in the dc gpio specifications sections. the i 2 c gpio pins also meet the above specs . 23. commands involving flash writes (0x01, 0x02, 0x03) and fl ash read (0x04) must be exec uted only within the same v cc voltage range detected at por (power on, or command 0x06) and above 2.7 v. [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 26 of 39 ac electrical specifications ac chip-level specifications ac gpio specifications table 10. 5-v and 3.3-v ac chip-level specifications parameter description min typ max units notes f 32k1 internal low-speed oscillator (ilo) frequency 15 32 64 khz calculations during sleep operations are done based on ilo frequency. t xrst external reset pulse width 10 ? ? us t powerup time from end of por to cpu executing code ? 150 ? ms sr power_ up power supply slew rate ? ? 250 v/ms table 11. 2.7-v ac chip-level specifications parameter description min typ max units notes f 32k1 internal low-speed oscillator (ilo) frequency 8 32 96 khz calculations during sleep operations are done based on ilo frequency. t xrst external reset pulse width 10 ? ? us t powerup time from end of por to cpu executing code ? 600 ? ms sr power_ up power supply slew rate ? ? 250 v/ms table 12. 5-v and 3.3-v ac general purpose i/o specifications parameter description min max unit notes t rise0 rise time, strong mode, cload = 50 pf, port 0 15 80 ns v dd = 3.10 v to 3.6 v and 4.75 v to 5.25 v, 10% to 90% t rise1 rise time, strong mode, cload = 50 pf, port 1 15 50 ns v dd = 3.10 v to 3.6 v, 10% to 90% t fall fall time, strong mode, cload = 50 pf, all ports 10 50 ns v dd = 3.10 v to 3.6 v and 4.75 v to 5.25 v, 10% to 90% table 13. 2.7-v ac gpio specifications parameter description min max unit notes t rise0 rise time, strong mode, cload = 50 pf, port 0 15 100 ns v dd = 2.4 v to 2.90 v, 10% to 90% t rise1 rise time, strong mode, cload = 50 pf, port 1 15 70 ns v dd = 2.4 v to 2.90 v, 10% to 90% t fall fall time, strong mode, cload = 50 pf 10 70 ns v dd = 2.4 v to 2.90 v, 10% to 90% [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 27 of 39 figure 12. definition of timing for fast/standard mode on the i 2 c bus ac i 2 c specifications parameter description standard mode fast mode units notes min max min max f scl i 2 c scl clock frequency 0 100 0 400 kbps fast mode not supported for v dd < 3.0 v. t hdsta i 2 c hold time (repeated) start condition. after this period, the first clock pulse is generated 4.0 ? 0.6 ? s t low i 2 c low period of the scl clock 4.7 ? 1.3 ? s t high i 2 c high period of the scl clock 4.0 ? 0.6 ? s t susta i 2 c setup time for a repeated start condition 4.7 ? 0.6 ? s t hddat i 2 c data hold time 0 ? 0 ? s t sudat i 2 c data setup time 250 ? 100 ? ns t susto i 2 c setup time for stop condition 4.0 ? 0.6 ? s t buf i 2 c bus free time between a stop and start condition 4.7 ? 1.3 ? s t sp i 2 c pulse width of spikes suppressed by the input filter ??050 ns i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 28 of 39 appendix ? examples of frequently used i 2 c commands sl no. requirement i 2 c commands [24] comment 1 enter into setup mode w 00 a0 08 2 enter into normal mode w 00 a0 07 3 load factory defaults to ram registers w 00 a0 02 4 do a software reset w 00 a0 08 w 00 a0 06 enter into setup mode do software reset 5 save current configuration to flash w 00 a0 01 6 load factory defaults to ram registers and save as user configuration w 00 a0 08 w 00 a0 02 w 00 a0 01 w 00 a0 06 enter into setup mode load factory defaults to sram save the configuration to flash. wait for time specified in ?capsense express commands? on page 17. do software reset 7 enable gp00 as capsense button w 00 a0 08 w 00 06 01 w 00 a0 01 w 00 a0 06 enter into setup mode configuring capsense buttons save the configuration to flash. wait for time specified in ?capsense express commands? on page 17. do software reset 8 read capsense button(gp00) scan results w 00 81 01 w 00 82 r 00 rd. rd. rd. select capsense button for reading scan result set the read point to 82h consecutive 6 reads get baseline, difference count and raw count (all two byte each) 9 read capsense button status register w 00 88 r 00 rd set the read pointer to 88 reading a byte gets status capsense inputs note 24. the ?w? indicates the write transfer and the next byte of data represents the 7-bit i2c address. the i2c address is assumed to be ?0? in the above examples. similarly ?r? indicates the read transfer followed by 7-bit address and data byte read operations. [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 29 of 39 ordering information note for die sales information, contact a local cypress sa les office or field applications engineer (fae). ordering code definitions table 14. key features and ordering information ordering code package diagram package type operating temperature capsense block gpios xres pin cy8c20110-ldx2i 001-09116 16 qfn [25] industrial yes 10 yes cy8c20110-sx2i 51-85068 16 soic industrial yes 10 yes cy8c20180-ldx2i 001-09116 16 qfn [25] industrial yes 08 yes cy8c20180-sx2i 51-85068 16 soic industrial yes 08 yes cy8c20160-ldx2i 001-09116 16 qfn [25] industrial yes 06 yes cy8c20160-sx2i 51-85068 16 soic industrial yes 06 yes CY8C20140-LDX2I 001-09116 16 qfn [25] industrial yes 04 yes cy8c20140-sx2i 51-85068 16 soic industrial yes 04 yes cy8c20142-sx1i 51-85066 8 soic industrial yes 04 no table 15. thermal impedances by package package typical ja [26] 16 qfn[1] 46 c/w 16 soic 79.96 c/w 8 soic 127.22 c/w table 16. solder reflow peak temperature package maximum peak temperature time at maximum peak temperature 16 qfn[1] 260 c 20 s 16 soic 260 c 20 s 8 soic 260 c 20 s notes 25. earlier termed as qfn package. 26. t j = t a + power ja. [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 30 of 39 package diagrams figure 13. 16-pin qfn 3 3 mm (sawn) figure 14. 16-pin (150--mil) soic 001-09116 *e 51-85068 *c [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 31 of 39 figure 15. 8-pin (150--mil) soic 51-85066 *d [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 32 of 39 acronyms acronyms used ta b l e 1 7 lists the acronyms that are used in this document. reference documents capsense express power and sleep considerations ? an44209 (001-44209) application notes for surface mount assembly of amkor's microleadframe (mlf) packages ? available at http://www.amkor.com . document conventions units of measure ta b l e 1 8 lists the unit sof measures. numeric conventions hexadecimal numbers are represented with all letters in uppercase wi th an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimals. table 17. acronyms used in this datasheet acronym description acronym description ac alternating current lvd low voltage detect cmos complementary metal oxide semiconductor mcu microcontroller unit dc direct current pcb printed circuit board eeprom electrically erasable programmable read-only memory por power on reset emc electromagnetic compatibility ppor precision power on reset gpio general-purpose i/o psoc ? programmable system-on-chip i/o input/output pwm pulse width modulator idac current dac qfn quad flat no leads ilo internal low speed oscillator rf radio frequency lcd liquid crystal display soic small-outline integrated circuit ldo low dropout regulator sram static random access memory led light-emitting diode xres external reset lsb least-significant bit table 18. units of measure symbol unit of measure symbol unit of measure c degree celsius mm millimeter hz hertz ms millisecond kbps kilo bits per second mv millivolts khz kilohertz na nanoampere k kilohm ns nanosecond lsb least significant bit % percent a microampere pf picofarad f microfarad v volts s microsecond w watt ma milliampere [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 33 of 39 glossary active high 1. a logic signal having its asserted state as the logic 1 state. 2. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opamp circuits. these are sc (switched capacitor) and ct (continuous time) blocks. these blocks can be interconnected to provide adcs, dacs, mu lti-pole filters, gain stages, and much more. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. application programming interface (api) a series of software routines that comprise an interface between a computer application and lower level services and functions (for exampl e, user modules and libraries). apis serve as building blocks for programmers that create softwa re applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the positive temperature coefficient of vt with the negative temperat ure coefficient of vbe, to produce a ze ro temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specific ally as, for example, full width at half maximum. bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perfo rm one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for i/o operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. a set of signals performing a common function and carrying similar data. typically represented using vector notation; fo r example, address[7:0]. 3. one or more conductors that serve as a co mmon connection for a group of related devices. clock the device that generates a periodic signal with a fixed frequen cy and duty cycle. a clock is sometimes used to synchroni ze different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 34 of 39 compiler a program that translates a high leve l language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in whic h the frequency is controlled by a piezoelectric crystal. typically a piezoelectric crystal is less sensitive to ambient te mperature than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data co mmunications, typically performed using a linear feedback shift register. similar calculations may be used for a variety of other purposes such as data compression. data bus a bi-directional set of signals used by a comp uter to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allo ws you to analyze the operation of the system under development. a debugger usually allows th e developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. digital blocks the 8-bit logic blocks that can act as a counter, timer, se rial receiver, serial transmitter, crc generator, pseudo-random number generator, or spi. digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog- to-digital (adc) converter pe rforms the reverse operation. duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. emulator duplicates (provides an emul ation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc device. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of eproms, pl us in-system erasability. non-volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be pr otected. a flash block holds 64 bytes. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, vo ltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconductors (now nxp semiconductors). i2c is an inter-integrated circuit. it is used to connect low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control el ectronics. i2c uses only two bi-d irectional pins, clock and data, both running at +5v and pulle d high with resistors. the bus operates at 100 kbits/second in standard mode an d 400 kbits/second in fast mode. glossary (continued) [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 35 of 39 ice the in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a device that introduces da ta into or extracts data from a system. interrupt a suspension of a process, such as the ex ecution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code execution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exis t with its own priority and individual isr code block. each isr code block ends with the reti in struction, returning t he device to the point in the program where it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a ty pical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low-voltage detect (lvd) a circuit that senses v dd and provides an interrupt to the system when v dd falls lower than a selected threshold. m8c an 8-bit harvard-architecture microprocessor. the microprocessor coordinates all activity inside a psoc by interfacing to the fl ash, sram, and register space. master device a device that controls the timing for da ta exchanges between two devices. or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external in terface. the controlled device is called the slave device . microcontroller an integrated circuit chip that is desi gned primarily for control systems and products. in addition to a cpu, a microcontroller typically includes memo ry, timing circuits, and i/o circuitry. the reason for this is to permit the realization of a co ntroller with a minimal quantity of chips, thus achieving maximal possible miniaturization. this in turn, reduces the volume and the cost of the controller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or mo re characteristics of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitting data. typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation bet ween the logical inputs and outputs of the psoc device and their physical counterparts in t he printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. glossary (continued) [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 36 of 39 port a group of pins, usually eight. power on reset (por) a circuit that forces the psoc device to reset when the vo ltage is lower than a pre-set level. this is a type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and programmable system-on- chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied measurand ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know state. see hardware reset and software reset. rom an acronym for read only memory. a data-storage device from which data can be read out, but new data cannot be written in. serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register a memory storage device t hat sequentially shifts a word either left or right to output a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, th e slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. the controlling device is called the master device. sram an acronym for static random access memory. a memory device where you can store and retrieve data at a high rate of speed. the term static is used because, after a value is loaded into an sram cell, it remains unchanged until it is explicitly al tered or until power is removed from the device. srom an acronym for supervisory read only memory. the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is syn chronized by a clock signal. glossary (continued) [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 37 of 39 tri-state a function whose output ca n adopt three states: 0, 1, and z (high-impedance). the function does not drive any value in the z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowin g another output to drive the same net. uart a uart or universal asynchronous receiver-tra nsmitter translates between parallel bits of data and serial bits. user modules pre-build, pre-tested hardw are/firmware peripheral functions that take care of managing and configuring the lower level analog and digital psoc blocks. user modules also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the re gisters in this bank are more likely to be modified during normal program execution and not just durin g initialization. registers in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning "voltage drain." the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of time. glossary (continued) [+] feedback
cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 document number: 001-54606 rev. *e page 38 of 39 document history page document title: cy8c20110, cy8c20180, cy8c20160, cy8c20140, cy8c20142 capsense ? express? ? button capacitive controllers document number: 001-54606 revision ecn orig. of change submission date description of change ** 2741726 slan/fsu 07/21/2009 new datasheet *a 2821828 sshh/fsu 12/4/2009 - add contents - added new electrical specs including f32k u, tpowerup, and several output current specs. - noted that the flash reads must al so be done at por voltage (previously only specified flash writes). *b 2892629 njf 03/15/2010 added t baketemp and t baketime parameters in absolute maximum ratings . changed 16 col to 16 qfn. added note on page 5. *c 3002214 slan 07/29/2010 changed the part number from cy8c21110 to cy8c20110 in features. minor edits. *d 3042142 arvm 09/30/10 included footnote for all gp1[ 1] and gp1[2] pins for all parts under pinouts section. removed f 32ku and t powerup rows from absolute maximum ratings table. included ?ac chip-level specifications? section under ?ac electrical specifications? section. under section "typical circuits" sche matic for "circuit 1 - five buttons and five leds with i2c interface" has been replaced. styles update. *e 3085081 njf 11/12/10 removed section ?2.7-v dc spec for i2c line with 1.8 v external pull-up?. added dc i 2 c specifications table.. updated units of measure, acronyms, glossary, and references sections. updated solder reflow specifications. no specific changed were made to i2c timing diagram. updated for clearer understanding. template and styles update. [+] feedback
document number: 001-54606 rev. *e revised november 19, 2010 page 39 of 39 all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c20110, cy8c20180 cy8c20160, cy8c20140 cy8c20142 ? cypress semiconductor corporation, 2009-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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